Intel GPU D-series (D270), explained: 480 GB of memory on one card, and what that buys you for AI inference

Intel used the Open Compute Project (OCP) Global Summit in San Jose, which runs from 12 to 15 October 2026, to give the full details of its inference GPU code-named Crescent Island. It is now the Intel GPU D-series, and Intel's product page labels the card "Intel GPU D270 | Inference-Optimized Data Center GPU". The newsroom post itself only says D-series.

It is built only for inference. A GPU for training has to do huge amounts of maths very fast. A GPU for inference, especially for large language models, spends much of its time waiting for numbers to arrive from memory, so Intel built this one around memory. The product page says the die area (the space on the silicon chip) was "reallocated from graphics and ray-tracing pipelines to Xe3P cores and matrix compute". Xe3P is Intel's newest GPU design; the card has 32 Xe3P cores and 256 XMX matrix engines, the parts that do the multiplications a model needs.

The headline numbers, from Intel's newsroom post: up to 480 GB of LPDDR5X memory, 1.5 TB/s of memory bandwidth and 1.3 petaflops of FP8 compute (FP8 means each number is stored in 8 bits) within a 350-watt power envelope. A footnote adds: "Intel branded PCIe card has 160GB LPDDR5x", and the design lets partners build their own cards "with flexible options up to 480GB memory".

LPDDR5X is the kind of memory used in laptops and phones. It is not HBM (High Bandwidth Memory, stacked right next to the chip), which the biggest data center GPUs use for speed. The result is a lot of room read at a moderate speed: 480 GB, at 1.5 TB/s. That single choice explains almost everything below.

Intel says the card supports models with up to 300 billion parameters on a single card and more than one trillion in an eight-GPU system, that customer sampling is underway, and that it runs vLLM and the open PyTorch tools, with SGLang and OpenAI Triton listed on the product page "where approved". It has not given a price or a date for general sale.

A language model writes one token at a time. To produce each token, the chip must multiply the newest token by every weight in the model (the numbers it learned in training); what it needs from the earlier tokens comes from the KV cache, described below. The maths for one token is small; the problem is that all those weights live in memory and have to be read again for every single token. A 70-billion-parameter model stored at one byte per weight is 70 GB, so writing 20 tokens a second means reading 1.4 TB a second.

That gives a simple rule. For one conversation, the most tokens a second you can get is the memory bandwidth divided by the bytes read per token. On the D-series that is 1.5 TB/s divided by the size of the model, plus the KV cache, which comes next.

The KV cache (key-value cache) is the model's working memory of the conversation so far. The model stores two lists of numbers for every earlier token, so it does not redo that work, and it reads them all again for each new token. It grows with every token and every user has their own. For Qwen2.5-72B, a real open model, the config file gives 80 layers, 8 key-value heads and 128 numbers per head, which at 2 bytes each is 327,680 bytes per token. One conversation of 4,096 tokens holds 1.34 GB.

So memory size decides how many conversations can be held at once, and bandwidth decides how fast they all move. More memory never makes a single answer faster. I measured the rule before trusting it.

Every fact about the card comes from Intel's newsroom post and D-series product page, read on 13 October 2026 and linked below. intel.com refused a plain download (HTTP 403), so I read the pages through a browser fetch instead of saving copies. The NVIDIA numbers come from NVIDIA's RTX PRO 6000 Blackwell Server Edition page, and Apple's 120 GB/s from Apple's MacBook Air M4 spec page.

Intel has not said whether its 1.3 petaflops of FP8 assumes sparsity (skipping zeros), and NVIDIA's 2 petaflops is as NVIDIA lists it, so I did not compare compute. It barely matters here: while writing tokens, every case on this page runs out of bandwidth long before compute. Reading a long prompt is the opposite, limited by compute, and I did not model it.

I did not run a D-series card. The bandwidth and batching measurements are real and were made on my Mac; the D-series figures are arithmetic built on that rule and on Intel's listed numbers. I will update this page when someone publishes measured results on a shipping card.